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Signals/Connections
Table 2-10. Host Interface (Continued)
Signal Name
HACK/HACK
Type
Input
State During
Reset 1, 2
Ignored Input
Signal Description
Host Acknowledge— When the HI08 is programmed to interface with a
single host request host bus and the HI function is selected, this signal is the
Host Acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is programmable, but is configured as active-low (HACK) after
reset.
HRRQ/HRRQ
PB15
Output
Input or
Output
Receive Host Request— When the HI08 is programmed to interface with a
double host request host bus and the HI function is selected, this signal is the
Receive Host Request (HRRQ) output. The polarity of the host request is
programmable, but is configured as active-low (HRRQ) after reset. The host
request may be programmed as a driven or open-drain output.
Port B 15
When the HI08 is configured as GPIO through the HPCR, this signal is
individually programmed through the HDDR.
Notes: 1.
2.
In the Stop state, the signal maintains the last state as follows:
? If the last state is input, the signal is an ignored input.
? If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are
tri-stated.
The Wait processing state does not affect the signal state.
2.8 Enhanced Synchronous Serial Interface 0
There are two synchronous serial interfaces (ESSI0 and ESSI1) that provide a full-duplex serial
port for serial communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the
Motorola serial peripheral interface (SPI).
Table 2-11. Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal
Name
SC00
Type
Input or Output
State During
Reset 1, 2
Ignored input
Serial Control 0
Signal Description
Functions in either Synchronous or Asynchronous mode. For Asynchronous
mode, this signal is the receive clock I/O (Schmitt-trigger input). For
Synchronous mode, this signal is either for Transmitter 1 output or Serial I/O
Flag 0.
PC0
2-12
Port C 0
The default configuration following reset is GPIO. For PC0, signal direction is
controlled through the Port C Direction Register (PRRC).
This signal is configured as SC00 or PC0 through the Port C Control Register
(PCRC). This input is 5 V tolerant.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
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